30 n-channel logic level enhancement mode field effect transistor features 30v , 40a , r ds(on) =13.5m @v gs =10v. super high dense cell design for extremely low r ds(on) . high power and current handling capability. to-251 & to-252 package. absolute maximum ratings (tc=25 c unless otherwise noted) parameter symbol limit unit drain-source voltage v ds v gate-source voltage v gs 20 v drain current-continuous -pulsed i d 40 a i dm 120 a drain-source diode forward current i s 40 a maximum power dissipation p d w operating and storage temperature range t j ,t stg -55 to 150 c thermal characteristics thermal resistance, junction-to-case thermal resistance, junction-to-ambient r / jc r / ja 2.5 50 /w c /w c ? r ds(on) =20m @v gs =4.5v. ? CED61A3/ceu61a3 @tc=25 c derate above 25 c 50 0.4 w/ c s g d ceu series to-252aa(d-pak) ced series to-251(l-pak) g g s s d d 6-62 jan. 2003 6
CED61A3/ceu61a3 electrical characteristics (t c 25 c unless otherwise noted) = parameter symbol condition min typ max unit off characteristics drain-source breakdown voltage bv dss v gs = 0v, i d= 250 a 30 v zero gate voltage drain current i dss v ds = 30v, v gs = 0v 1 a gate-body leakage i gss v gs = 20v, v ds = 0v 100 na on characteristics a gate threshold voltage v gs(th) v ds = v gs ,i d 250 a 13 v drain-source on-state resistance r ds(on) v gs = 10v, i d =20a 11 13.5 m ? v gs =4.5v,i d =18a 16.5 20 m ? on-state drain current i d(on) v ds = 10v, v gs =10v 40 34 a s forward transconductance fs g v ds = 10v, i d =26a dynamic characteristics b input capacitance c iss c rss c oss output capacitance reverse transfer capacitance v ds =15v, v gs =0v f=1.0mh z 1200 p f 480 p f p f 130 switching characteristics b turn-on delay time rise time turn-off delay time t d(on) t r t d(off) t f v dd =15v, i d =40a, v gs = 10v r gen =24 ? 18 30 ns ns ns ns 25 50 45 90 75 130 total gate charge gate-source charge gate-drain charge q g q gs q gd nc nc nc c fall time 6-63 4 19 5 9 23 v ds =15v,i d =40a v gs =5v 6
parameter symbol condition min typ max unit electrical characteristics (t c =25 c unless otherwise noted) drain-source diode characteristics diode forward voltage v sd v gs =0v,is=26a 1.3 0.9 v a notes b.guaranteed by design, not subject to production testing. a.pulse test:pulse width 300 3 s, duty cycle 2%. figure 1. output characteristics figure 2. transfer characteristics figure 4. on-resistance variation with drain current and temperature figure 3. capacitance v ds , drain-to source voltage (v) v gs , gate-to-source voltage (v) v ds , drain-to-source voltage (v) i d , drain current(a) c, capacitance (pf) drain-source, on-resistance i d , drain current (a) i d , drain current (a) [ [ 6-64 r ds(on) , normalized CED61A3/ceu61a3 2400 2000 1600 1200 800 400 0 5 10 15 20 25 30 ciss coss crss 0 010203040 25 c tj=125 c -55 c 1.8 1.6 1.4 1.2 1.0 0.8 0.6 v gs =10v 6 50 40 30 20 10 0 12 34 25 c tj=125 c -55 c 01234 v gs =3v 80 60 40 20 0 v gs =10,8,6,5,4v
CED61A3/ceu61a3 with temperature figure 6. breakdown voltage variation figure 5. gate threshold variation with temperature vth, normalized gate-source threshold voltage g fs , transconductance (s) v gs , gate to source voltage (v) bv dss , normalized drain-source breakdown voltage is, source-drain current (a) figure 7. transconductance variation with drain current i ds , drain-source current (a) figure 9. gate charge qg, total gate charge (nc) figure 10. maximum safe operating area v ds , drain-source voltage (v) figure 8. body diode forward voltage variation with source current v sd , body diode forward voltage (v) tj, junction temperature ( c) tj, junction temperature ( c) i d , drain current (a) 6-65 50 40 30 20 10 0 0102030 40 v ds =10v 50 10 1.0 0.1 0.4 0.6 0.8 1.0 1.2 1.4 1.15 1.10 1.05 1.0 0.95 0.90 0.85 0.80 -50 -25 0 25 50 75 100 125 150 v ds =v gs i d =250 3 a 200 100 300 10 1 0.5 0.1 1103060 r ds (o n) li m it v gs =10v single pulse tc=25 c d c 10ms 1 00ms 1 ms 1 0 0 3 s -50 -25 0 25 50 75 100 125 150 1.15 1.10 1.05 1.00 0.95 0.90 0.85 i d =250 3 a 10 0 2 4 6 8 010 203040 v ds =15v i d =40a 6
figure 11. switching test circuit figure 12. switching waveforms CED61A3/ceu61a3 t v v t t d(on) out in on r 10% t d(off) 90% 10% 10% 50% 50% 90% t off t f 90% pulse width 6-66 4 inverted transient thermal impedance 2 1 0.1 0.01 0.01 0.1 1 10 100 1000 10000 p dm t 1 t 2 square wave pulse duration (msec) figure 13. normalized thermal transient impedance curve 1. r / jc (t)=r (t) * r / jc 2. r / jc =see datasheet 3. t jm- t c =p*r / jc (t) 4. duty cycle, d=t1/t2 r(t),normalized effective d=0.5 0.2 0.1 0.05 0.02 0.01 single pulse v dd r d v v r s v g gs in gen out l 6
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